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75a, 600v magnum motor drives description the pw-83075p6, pw-84075p6 and pw-85075p6 are half- bridge drive modules containing isolated switch drivers, a pair of solid state switches, and an isolated power supply. in addition, the pw-84075p6 contains current sensing feedback and the pw-85075p6 contains a regenerative clamp protection circuit. the three modules can be used in any combination to create drives for brush, brushless dc, or ac induction motors. the cur- rent sense signal and logic inputs are compatible with dsp/microprocessors and/or fpga/asic circuits used to con- trol the motor drives. these modular drives are capable of oper- ating from either a 135vdc or 270vdc power source that is electrically isolated from the logic input signals. the modules are fault tolerant from output shorts, loss of any or all power sup- plies, and power supply sequencing. applications the high reliability and flexibility of these drives make them suit- able for military and aerospace applications. among the many applications are: actuator systems for primary and secondary flight controls on aircraft, fan and compressor motor drives for environment conditioning, pump motors for fuel and hydraulic fluid, antenna and radar positioning, and thrust vector position control of missiles, drones, and rpv?s. power supply sleep mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive vbus+ output vbus- ov amp regen status regen clamp + auto reset ov adj vcc vcc rtn regen clamp - 5k ? ov adj low ov adj high figure 1c. pw-85075p6 block diagram power supply sleep mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive vbus+ output vbus- current amp current amp r sense oc fault viref virsense_abs rsense+ rsense- vcc vcc rtn vdd vdd rtn virsense auto reset power supply vcc vcc rtn sleep mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive vbus+ output vbus- auto reset figure 1a. pw-83075p6 block diagram figure 1b. pw-84075p6 block diagram features ? 600 vdc drive for 270 vdc motors 75 amps @25c, 50 amps @85c operates with brushless, brush, and induction motors input to output ground isolation with floating output stage short circuit protection trapezoidal or sinusoidal compatible dsp/microprocessor compatible pw-83075p6 - half-bridge drive pw-84075p6 - half-bridge drive with current sense pw-85075p6 - half-bridge drive with regenerative clamp pw-8x075p6 m agnum m otor d rive s eries ? ?2001 data device corporation
2 table 1. pw-8x075p6 absolute maximum ratings parameter symbol value units ground isolation voltage (note 1) junction temperature, power devices storage temperature range peak output current (10 ms) continuous output current input logic voltage logic power-in supply voltage drive supply voltage v iso tj tcs i peak i o upper, lower, disable/reset, sleepmode, auto reset v cc v bus + to v bus - 2500 +150 -65 to +125 150 75 5.5 5.5 600 vdc c c a a reference input voltage v iref v dd + 0.5 vdc vdc vdc vdc table 2. pw-8x075p6 specifications ( v cc = v dd = 5v unless otherwise specified, tc = -55c to +100c for min, max values, tc = +25c for typical values.) parameter output stage drive supply voltage (motor) output switch transistors (each) continuous current drive turn-on energy per pulse turn-off energy per pulse peak current short circuit trip current (note 1) output voltage drop (igbt) flyback diode forward voltage reverse recovery time @ t j = +125 c reverse recovery peak current reverse leakage current @ t j = +25 c reverse leakage current @t j = +125 c v bus + to v bus - i o e t- o n e t- o f f i peak i sc v ce(sat) v f t rr irm i r i r unipolar/bipolar +25 c case +85 c case v ce = 270v, i = 50a t j = +125 c v ce = 270v, i = 50a t j = +125 c +85 c case, 15 ms 5 ? i o = 50a i o = 50a i o = 50a di/dt = 480a/? i f = 50a (90 c) vbus = 480vdc vbus = 480vdc symbol test conditions 200 min typ max units 270 4.0 2.4 350 2.2 1.7 175 19 30 600 75 50 100 400 2.6 1.9 33 325 17 vdc a a mj mj a a vdc vdc ns a ? ma intermittent case operating temperature continuous case operating temperature junction temperature, other components tc t ci -55 to +100 -55 to +125 c c t j +125 c ns ns ? ns ns ms khz 650 1800 45 200 200 35 430 790 33 3.7 t d (on) t d (off) t s d t r t f tsleepu fpwm output switching characteristics (see figure 5) turn-on propagation delay turn-off propagation delay disable propagation delay turn-on rise time turn-off fall time sleep_mode delay output switching frequency 150 740 25 100 140 0 vdc vdc vdc ? na ? ? ? ma vdc vdc ? ma 3.15 2.45 2.1 24 100 24 1.5 0.8 0.5 2.5 1.6 0.9 23 0.1 0 23 0 1.4 0.1 1.55 0.9 0.4 22 0 22 1.3 2.4 0.4 v cc = 4.5v vin = v cc vin = 0v vin = v cc vin = 0v vin = v cc vin = 0v v cc = 4.5v v cc = 4.5v vin = v cc vin = 0v vih vil vhyst iih iil iih iil iih iil vih vil iih iil control inputs upper, lower, disable/reset auto reset high level input voltage low level input voltage hysteresis voltage upper, lower high level input current low level input current reset/disable high level input current low level input current auto_reset high level input current low level input current sleep_mode high level input voltage low level input voltage high level input current low level input current note 1: from v cc-rtn to v bus +, v bus -, output, regen clamp+, r sense +, r sense -.
3 units max typ min symbol test condition parameter table 2. pw-8x075p6 specifications (tc = +25c, v cc = v dd = 5v unless otherwise specified, tc = -55c to +100c for min, max values) current amplifier v irsense gain v irsense gain error v irsense offset v irsense offset drift v irsense gain % v irsense offset % v irsense offset % drift i_vabs gain i_vabs gain error i_vabs offset i_vabs offset drift i_vabs gain % i_vabs offset % i_vabs offset % drift delay time bandwidth linear range oc_fault trip level trip delay time reference voltage current input reference voltage input gvout evout vos tcvos gvout% vos%v iref tcvos% gvabs evabs vosabs tcvosabs gvout% vosabs% v iref tcvosabs% tdelay fbw irange ioc t ioc iviref v iref v iref = 5.0v v iref = 5.0v v iref = 5.0v 0a = vref/2 0a = 0v v iref = 5.0v v iref = 5.0v 0a = 0v -55 to 100 c -55 to 100 c -55 to 100 c -55 to 100 c -55 to 100 c -55 to 100 c -55 to 100 c -6 -30 -90 -0.6 -18 -8 -131 -90 -2.6 -18 20 ?5 4.0 29.76 0.595 59.52 1.19 9 30 ?0 ?5 66 0.26 6 30 110 0.6 22 8 131 110 2.6 22 20 ?5 1 v dd mv/a % mv ppm/ c %v iref /a %v iref ppm of v iref / c mv/a % mv ppm/ c %v iref /a %v iref ppm of v iref / c ? khz a a us ma vdc max typ min symbol test condition parameter table 4. pw-84075p6 specifications (tc= +25c v cc = v dd = 5v unless otherwise specified) units 5.5 200 20 5 11 136 10 4.5 8 v cc , v dd icc idd sleep mode f pwm = 25khz power & logic supply (-55 to 100 c) voltage logic supply current current amplifier supply current v ma ma ma note 1: v bus + to v bus - must be 10v (during short circuit) for short circuit protection to operate. note 2: auto_reset tied to sc_fault c in-lbs oz (gr) c/w c/w c c c +250 3 3.1 (88) 0.55 0.87 +150 +100 +150 0.5 0.8 -55 -55 -65 mechanical maximum lead soldering temp mounting torque weight thermal maximum thermal resistance - igbt - diode junction temperature range case operating temperature case storage temperature ts jc jc tj tc tcs each output switch ? ms ms ns ms 202 3.0 100 1.0 200 40 (see note 2) tdead tdoff.auto tdon.auto tpw.reset tcycle.auto upper-lower deadtime auto_reset delay to output off auto_reset delay to output enabled reset pulsewidth to clear sc_fault cycle time between auto_reset retries ? ma 24 23 10 22 5 vo = v cc vo = 0.4v iscflth iscfltl control outputs sc_fault high level output current low level output current 15 0.2 4 iocflth iocfltl vo = v dd vo = 0.8v oc_fault (-55 to 100 c) high level output current low level output current ua ma v ma ma 5.5 200 5 11 110 4.5 sleep mode f pwm = 25khz v cc , v dd icc power and logic supply voltage logic supply current table 3. pw-83075p6 specifications (tc= +25c)
introduction the pw-8x075p6 is a universal modular half-bridge motor drive intended for use with brush, brushless dc and ac induction motors in aerospace applications. the isolation barrier, which separates the power and control stage, attenuates the ground noise generated from high speed, high power switching. all signals from the control to the power sections are isolated from power and ground of the other section. this eliminates false triggering of the input signals and the need for creative grounding schemes. the isolation barrier also allows the user to operate the output stage from either unipolar or bipo- lar power supplies without level shifting the input signals. a built in power supply located in the control stage provides power to all electronics in the power stage. this eliminates the need for refresh cycles or external power supplies for the gate drive circuitry and allows switching duty cycles from 0 - 100%. in addition, the pw-84075p6 provides current sensing of either motor current or dc bus current. this current signal can be used as a feedback signal in a servo drive to create a torque loop. the output power transistors on all modules are protected from a short circuit applied to the output pin. when a short circuit con- dition is detected, the output transistor is shut down and a flag ?sc_fault? is made active (logic low (l)) indicating a short has occurred. all output power transistors can be protected from regenerative bus overvoltage when utilizing dynamic braking with the addition of one pw-85075p6 module. when an overvoltage condition is detected, the overvoltage switch is enabled and an external (user supplied, application specific) load dump resistor is connected across the high voltage bus. during an overvoltage condition, the status flag ? regen status ? is active (logic low (l)) indi- cating an overvoltage condition is occurring. module and i/o operation 4 max typ min symbol test condition parameter table 5. pw-85075p6 specifications ( v cc = v dd = 5v unless otherwise specified, tc = -55c to +100c for min, max values, tc = +25c for typical values.) units over voltage transistor continuous current drive peak current output voltage drop (igbt) reverse leakage @ t j = +25 c reverse leakage @ t j = +125 c over voltage flyback diode reverse leakage @ tc = +25 c reverse leakage @ tc = +125 c over voltage trip trip level hysteresis io i peak v ce ( sat ) ir ir ir ir vtrip vhyst +25 c case +85 c case +85 c case, 15 ms 600 vdc 600 vdc 2.0 35 30 60 3.0 250 1.0 a a a vdc ? ma 480 vdc 480 vdc no external adjustments 358 34 20 1 400 40 50 7 440 45 ? ma vdc vdc thermal maximum thermal resistance jc over voltage switch 0.8 1.2 c/w 5.5 250 5 11 137 4.5 v cc icc sleep mode f pwm = 25khz power and logic supply voltage current v ma ma upper, lower (inputs) the upper and lower are active high cmos schmitt-trigger inputs and control the gate drives of the output transistors. (ttl compatibility requires external pull-up resistors) each input is electrically isolated from the output. a deadband, as shown in figure 2, between upper and lower inputs is necessary to prevent output cross conduction. sc fault (output) the sc fault is an active low open collector output signal that indicates when the output of the module has experienced a short circuit condition with faults cleared. the signal is inactive at a logic high (h). the signal goes active, logic low (l), when a short circuit condition is detected. see short circuit protection for more detail. sc fault remains active (l) until disable/reset is made active (l). disable / reset (input) disable/reset is an active low cmos schmitt-trigger input that is active when a logic low is applied. when disable/reset is held active it does two things: 1.) resets the sc fault (if it was active), and 2.) disables the output (makes the output high impe- dence). if this line is used solely to clear sc fault then it only needs to be pulsed active then inactive. the width of the active pulse must be at least the width of the trip reset pulse (100ns) to ensure that sc fault is cleared properly. when this line is inac- tive, the output is allowed to respond to the other control lines of the module (upper, lower, sleep). note: ttl compatibility requires an external pull-up resistor. auto reset (input) when the auto reset, active low (l) is tied to sc fault, the protection circuit will reset automatically after the short circuit fault has occurred, enabling the output to respond to the input com- mands. see short circuit protection for more detail. vdc vdc k ? ? ? 15.6 0.4 4.8 15 0.2 4.75 36 48 13.8 4.2 no load no load vohstatus volstatus rstatus tdon.status tdoff.status regen status (ref. to regen clamp-) high level output voltage low level output voltage output resistance vtrip rise to status on delay vtrip fall status off delay
5 tdead = 1.0 ? min. 50% upper lower 50% 50% 1.0 ? min. 50% figure 2. pw-8x075p6 dead band requirement short circuit protection the pw-8x075p6 modules have provisions for complete short cir- cuit protection from either a hard or soft short to the v bus + or v bus - lines. each output transistor on all pw-8x075p6 modules is pro- tected from a hard (direct, low impedence) short to the v bus + or v bus - lines by circuitry that detects the desaturation voltage for that transistor during a short condition. once a hard short circuit con- dition is detected, the active output transistors are shut down and sc fault output is set active (logic low (l)). the sc fault sig- nal can be used by the controller as a signal to initiate a fault rou- tine to reset or shut down the system. the disable/reset can be used to shut down the gate drivers if a short persists. if the auto reset is tied to sc fault, the circuit will automati- cally reset when a fault occurs. this inactivates sc fault and reactivates the output transistor within 40 to 100ms. if the short is still present, the circuit will repeat the shut down and automat- ically reset until the short is clear. protecting against a soft-short requires using a pw-84075 for current sensing and external cir- cuitry. when a soft-short occurs, the external circuit can set disable/reset low (l) to shut down the gate drivers. sleep mode (input) the sleep mode input turns the internal power supply on or off. a logic high (h) on the sleep mode input disables the internal power supply, disabling the motor drive output. no damage will occur to the motor drive during turn on or turn off of the power sup- ply. additionally, no special power up sequence is required. a logic low (l) enables the power supply and allows the motor drive to operate normally. the upper and lower logic gate driver inputs should not be active while transitioning in and out of sleep mode. if the upper and lower logic inputs must be active while entering sleep mode then disable/reset must be held active while coming out of sleep mode. v cc ,v cc-rtn (inputs) the v cc and v cc-rtn are power connections that supply input power to the internal power supply, the gate drive and fault con- trol circuits. v bus +, v bus - (inputs) v bus + and v bus - are the high voltage power connections to the output stage. the high voltage can be either unipolar (+v and ground) or bipolar (+/- v). care must be taken to ensure that the transient bus voltage v bus at the module terminals never exceeds the absolute maximum excursions during switching. external capacitor filtering will be required (see ddc applications note an/h-7). output (output) the output connects to one input of the motor and applies v bus +, v bus -, or high impedance to the motor based on the state of the control inputs. it is capable of sourcing or sinking up to 75 amps, and the output can withstand a short circuit to v bus + or v bus - with- out any damage by automatically turning itself off (zstate). v dd ,v dd rtn (applies to the pw-84075p6 only) the v dd and v dd rtn supply input power to the current amplifi- er. v irsense (output) (applies to pw-84075p6 only) the voltage on the v irsense pin represents current passing through rsense in the direction shown in the block diagram. this v irsense voltage is scaled by the input voltage at v iref , where v irsense = (v iref /2) + (v iref /168) * i_rsense note: i_rsense is current through rsense. zero amps in rsense is indicated when v irsense = v iref /2. a volt- age greater (less) than v iref /2 indicates a positive (negative) cur- rent flow through rsense with a value defined by the v irsense equation. v irsense is electrically isolated from the output stage. a positive (negative) current flow from r sense + to r sense - produces a positive (negative) voltage measurement (see figure 2a). when the power supply is shut down (sleep mode input high), the voltage at v irsense will indicate 0v. v iref (input) (applies to pw-84075p6 only) a precision voltage reference from an external source is connect- ed to the v iref pin to set the output voltage scale for v irsense and v irsense_abs . note: the accuracy of the v irsense and v irsense_abs outputs are subject to the accuracy and temperature coefficient of v iref . these must be taken into account in calculating the overall accuracy of v irsense . r sense +, r sense - (inputs) (applies to pw-84075p6 only) the r sense + and r sense - pins are conected to an internal shunt resistor and monitoring circuitry. these pins can be connected anywhere within the isolation restrictions on the pins (600v to power pins, 2500v to logic pins). these pins are typically con- nected in series with the output, v bus + or v bus -, to measure motor drive current. 0 20 55 50 45 40 35 30 25 15 95 85 75 65 55 105 115 125 5 khz 25 khz 15 khz 20 khz 10 khz 60 65 70 75 45 35 25 -55 figure 3. pw-8x075p6 output phase current vs. maximum operating case temperature v bus + = 270 vdc duty cycle = 50% tj(max) = 150 c maximum operating case temperature, tc c output phase current, i avg (amps)
10 100 1000 350 375 400 425 450 475 500 525 550 trip voltage, (vdc) resistance, (kohms) ov switch on ov switch off v h vmin vmax figure 4a. pw-8x075p6 typical over voltage trip vs. ov adjust setting with an external ov adjust resis- tor connected to ov_adj_high figure 4b. pw-8x075p6 typical over voltage trip vs. ov adjust setting with an external ov adjust resis- tor connected to ov_adj_low note : v h = hysteresis voltage note : v h = hysteresis voltage v irsense_abs (output) (applies to pw-84075p6 only) v irsense_abs output voltage is the absolute value of the v irsense volt- age signal. v irsense_abs is zero volts when there is no current flow- ing through the rsense resistor. it will increase towards the value of v iref as the current in rsense approaches either -85 or +85 amps (measurement limits of v irsense ). v irsense_abs is an open source output and is ? wire-or-able ? . when two or more v irsense_abs outputs are ? wire-or-ed ? , the highest voltage will appear on the common signal. a typical use for combining these outputs is for determining when an overload condition has occurred. the v irsense_abs voltage is scaled by the input voltage v irsense where: v irsense_abs = 2 x [v irsense - v iref /2] oc fault (output) (applies to pw-84075p6 only) oc fault is an active low open drain output. oc fault goes active when the current flowing through rsense has exceeded the oc_fault trip level. this signal is not latched like sc fault, and goes inactive as soon as the overcurrent condition stops. regen status (output) (applies to pw-85075p6 only) the regen status pin is referenced to regen clamp-. it indicates the state of the regen clamp switch (h = on, l = off). an external opto-isolator input can be connected between regen status and regen clamp- to translate this status to logic cir- cuits if desired. the regen status output is connected to the 0v amplifier through a 5k resistor. when the regen clamp switch is active (inactive), the 0v amp sources +15v (0v) through the 5k resistor. (see fig. 1c) ov_adj (input) (applies to pw-85075p6 only) the pw-85075p6 is internally set for a trip voltage of 400v. to set a different trip voltage, an external ov adjust resistor (ref. r21on figures 9a and 9b) is connected from the ov_adj pin to either the ov_adj_high or the ov_adj_low pin. this resistor should be selected for the trip voltage, vmax, for the regen clamp switch to turn on. (see figures 4a and 4b) note: ov_adj_low (pin 22), ov_adj_high (pin 17), and ov_adj (pin 20) are available on the control side of the module for ease of connecting the external ov adjust resistor. regen clamp+, regen clamp- (outputs) (applies to pw-85075p6 only) (ref. r20 on figures 9a and 9b) an external load dump resistor is connected between regen clamp+ and v bus +. when v bus + reaches the over voltage trip level set by the ov_adj, the internal clamp circuit will apply the load dump resistor from v bus + to the regen clamp-, thereby dissipating the regenerative energy in the external resistor. in addition, regen clamp- has to be externally connected to v bus - for the clamp circuit to work properly. this connection (pcb traces or wire) has to be able to carry the regenerative current. upper/lower 50% t f t r output 90% 10% 50% t d (on) t d (off) figure 5. pw-8x075p6 input/output timing relationship 6 1 10 100 1000 10000 0 50 100 150 200 250 300 350 400 trip voltage, (vdc) resistance, (kohms) ov switch on ov switch off v h vmin vmax
7 x = indicates that this input is irrelevant z = high impedance (off). * = fault will disable the transistor that caused the fault. the output state could be z or on. 10% 90% t d (off) 10% 90% 5% v bus o i d (on) t r f t t upper / lower on e off e t on figure 7. output characteristics position command position error velocity command velocity error torque command torque error current error amp pwm pw-8x075p6 3-module set 3-phase motor torque loop velocity loop position loop + - + - + - motor angle / position information (hall / resolver / encoder) velocity error amp position error amp figure 6. typical position and velocity control loop power dissipation (see figure 7) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. consider the following operating conditions tcase = 85 c vbus = +270v i o = 40a (see figure 7);) ton = 50 s (see figure 7); t = 100? ( period ) v ce(sat) = 2.2v (see table 2) t r = 200ns (see figure 7); t f = 200ns (see figure 7) fpwm = 10khz (switching frequency) v f is the diode forward voltage, table 2, i o = 50a, t c = +25 c v f (avg) = 1.35v t j max = 150 c (table 2, t j ) jc = 55 c / w (table 2) 1. conduction losses (p c ) p c = i o x v ce(sat) x (ton / t) p c = 45a x 2.2v x (50? / 100?) p c = 44w 2. switching losses (p s ) p s = (e on + e off ) x fpwm e on = ( e t-on x (vbus / 270) x ( i o /50a) ) e on = ( 4.0 x (270 / 270) x (40 / 50)) e on = 3.2 mj e off = (e t-off x (v bus /270) x (i o /50)) e off = (2.4 mj x (270/270) x (40/50)) e off = 1.92 mj p s = 10000 x (.0032 + .00192) p s = 51.2w 3. flyback diode losses (pdf) pdf = i o x v f (avg) x (1- (ton / t)) pdf = 50a x 1.35v x [1 - (50? / 100?)] pdf = 33.8w transistor power dissipation (p t ) p t = p c + p s = 95.2w to calculate the maximum power dissipation of the output tran- sistor / diode pair as a function of the case temperature, use the following equation. p max = ((t jmax - t case ) / jc ) 118w = ((150 c - 85 c) / 0.55 c / w ) disable/ reset lower z 1 0 x bus- 0 bus+ x z 0 0 z 1 1 1 * 1 1 * z 1 table 6. pw-8x075p6 truth table 0 x x 0 1 x x 1 1 0 x upper sleep- mode sc-fault out 0 0 x x 0 x 1 0 1 1 x x 0 x x 0
8 0.4 0.6 0.8 1.0 1.2 1.4 1.6 25 50 75 100 125 150 i = 100a c t - degrees c j v - normalized ce(sat) i = 50a c i = 25a c 0 100 1 10 100 600 0.1 i c - amperes v ce - volts t j = 125 c dv/dt < 5v/ns 200 300 400 500 600 200 0 vfr - volts dl/dt - a/us 20 0 4 8 12 16 400 600 800 1000 1200 t vj = 25 c i f = 60a v fr t fr 0 200 400 600 800 1000 tfr - nanoseconds 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 0 4 8 12 16 20 24 t = 125?c j (on) (off) e e e - millijoules i - amperes c e - millijoules (off) (on) 0.5 1.0 40 60 100 180 0 current - amperes voltage drop - volts 2.0 1.5 2.5 20 80 120 140 160 t vj = 150 c t vj = 25 c t vj = 100 c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 40 80 120 160 i rm t - degrees c j normalized irm/qrr 1.4 q r figure 8a. temperature dependence of v ce(sat); figure 8b. dependence of e on and e off on i c figure 8c. turn-off safe operating area figure 8d. maximum forward voltage drop figure 8e. peak forward voltage v fr and forward recovery time t fr figure 8f. junction temperature dependence of i rm and q r characteristic curves for output power transistors on pw-8x075p6
9 1 10 100 1000 1 2 3 4 5 0 qrr - nanocoulombs dl/dt - a/us t vj = 100 c v r = 350v i f = 60a 0 200 400 600 200 400 600 dl/dt - a/s irr - nanoseconds 800 t = 100 ? c v = 350v i = 60a r vj f 0 20 40 60 1000 200 400 600 800 dl/dt - a/s irm - amperes 80 max t = 100 ? c v = 350v i = 60a r vj f figure 8g. maximum reverse recovery charge figure 8h. peak reverse recovery current figure 8i. maximum reverse recovery time characteristic curves for output power transistors on pw-8x075p6
10 20us pulse width 0.1 1 10 10 1 100 1000 ic, collector-to-emitter current (a) vce, collector-to-emitter voltage (v) t j = 150 c t j = 25 c 20 i c = 62a i c = 31a i c = 16a 80us pulse width 0 -20 -40 -60 160 140 120 100 40 60 80 t j , junction temperature ( c) 1.0 1.5 2.0 vce, collector-to-emitter voltage (v) 20 070 50 30 40 60 10 0 10 total switching losses (mj) ic, collector-to-emitter current (a) 20 30 t j = 150 c v cc = 480v 50 40 60 0 10 20 30 25 50 75 100 125 150 t c , case temperature ( c) maximum dc collector current (a) 20 i c = 62a i c = 31a i c = 16a v cc = 480v 0 -20 -40 -60 160 140 120 100 40 60 80 1 10 100 total switching losses (mj) t j , junction temperature ( c) vce, collector-to-emitter voltage (v) 10 1 100 1000 1 10 100 1000 t j = 125 c ic, collector-to-emitter current (a) safe operating area figure 9a. typical output characteristics figure 9b. maximum collector current vs. case temperature figure 9c. collector-to-emitter voltage vs. junction temperature figure 9d. typical switching losses vs. junction temperature figure 9e. typical switching losses vs. collector-to-emitter current figure 9f. turn-off safe operating area characteristic curves for overvoltage switch transistors on pw-85075p6
11 table 7: pin assignments 2 v cc v cc v cc pin # functions description 1 disable/reset disable/reset disable/reset 3 upper upper upper 4 v cc-rtn v cc-rtn v cc-rtn 5 lower lower lower 6 sleep mode sleep mode sleep mode 7 sc fault sc fault sc fault 8 auto reset auto reset auto reset 17 n/c v iref ov_adj_high* 18 n/c v irsense regen status 19 n/c v irsense_abs n/c 20 n/c v dd ov_adj 21 n/c v dd-rtn n/c 22 n/c oc fault ov_adj_low* pw-83075p6 pw-84075p6 pw-85075p6 25 n/c r sense - regen clamp+ 26 n/c r sense + regen clamp- 27 v bus + v bus + v bus + 28 output output output 29 v bus - v bus - v bus - applications: position or velocity control using dsp figure 9a shows an example of position and/or velocity control hook-up with inner torque loop using the digital signal processor (dsp) for motor control. using software, the dsp can be imple- mented with one of several motor control algorithms such as foc (field oriented control) with svm (space vector modula- tion). torque hook-up using uc-1625 motor controller figure 9b shows an example of torque control loop with regen- erative clamp protection using uc-1625, two pw-84075p6, and one pw-85075p6. two pw-84075p6 ( ? bridge with current sense) sense the current in motor phase a and c. v irsense_abs pins on each of the pw-84075p6 can be tied together to gener- ate a single composite analog output which is compared to the torque commanded input to produce an error signal. uc1625 uses this error signal to regulate the output current (or torque) by controlling the duty cycle of the output transistors. for the case when a resolver is available instead of hall-effect devices, the circuit shown in figure 9c converts the resolver (sin and cos) signals to hall signals which can be used to commutate the output transistors. hall signal commutation the hall a, b, c signals are logic signals from the motor hall- effect sensors. the uc-1625 uses a phasing convention referred to as 120 degree spacing; that is, the output of ha is in phase with motor back emf voltage vab, hb is in phase vbc, and hc is in phase with vca. logic 1 (or high ) is defined by an input greater than 2.4vdc or an open circuit to the controller; logic 0 (or low) is defined as any hall voltage input less than 0.8vdc. the uc-1625 will operate with hall phasing of 60 or 120 elec- trical spacing. if 60 commutation is used, then the output of hc must be inverted as shown in figures h1 and h2. in figure h1 the hall sensor outputs are shown with the corresponding back emf voltage they are in phase with. 23 n/c n/c n/c 24 n/c n/c n/c power control hall-effect sensor phasing vs. motor back emf for cw rotation (120 commutations) 300 0 60 120 180 240 300 360 /0 60 v ab v bc v ca back emf of motor rotating cw cw ha hb hc hc in phase with v ab in phase with v bc in phase with v ca in phase with v ac (60 ? ) s hc ha 120 n hb 120 n hc 120 remote position sensor (hall) spacing for 120 degree commutation 60 60 remote position sensor (hall) spacing for 60 degree commutation s ha hb hc figure h1. hall phasing figure h2. hall sensor spacing * connection for external ov adjust resistor only.
12 1 3 5 7 2 4 6 8 17 19 21 18 20 22 0.69 max (17.526) 2.89 max (73.40) 1.48 max (37.59) pw-8x075p6-xxxx m agnum m otor d rive 29 28 27 26 25 0.125 ( 3.17) 0.200 (5.08) side view top view 23 24 16 eq. pin 0.100 centers (2.54 centers) 0.025 sq. (16 places) (0.635) molded in metal insert (2 places) 0.250 x 0.03(thk) (5 places) (6.35 x 0.76) 0.220 (5.58) 0.115 dia (#4 screw) (2 places) (2.92 dia) 2.52 (64.00) 2.36 (59.94) 0.100 (2.54) s/n xxxx d/c xxxx tm 0.940 (23.87) 0.738 (18.74) 0.250 (6.35) 0.100 (typ) (2.54) 0.35 (8.89) 0.120 (3.04) .006 1.100 (27.94) 1.000 (25.40) 0.900 (22.86) 0.800 (20.32) 0.200 (5.08) 0.300 ( 7.61) 0.100 (2.54) 0.250 (6.35) 1.140 (28.95) 0.570 (14.48) 2.645 (67.183) 0.250 (6.35) 0.230 (5.84) 0.020 (0.508) (typ) center line center line 0.120 (3.04) 0.550 (13.97) figure 8. pw-8x075p6 outline notes: 1. dimensions are in inches (mm). mounting considerations: 1. minimum spacing center line to center line - 1.5 inches (38.1 mm) 2. mounting torque using 4-40 stainless steel mounting screws - 5 to 6.5 in.-lbs.
13 +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn motor sleep mode v cc upper lower sc fault disable/reset v cc-rtn regen status vbus+ output vbus- regen clamp+ upper lower sc fault oc fault i_vout vref upper lower sc fault i_vout vref vbus+ output vbus- rsense+ rsense- vbus+ output vbus- rsense+ rsense- pw-85075p6 pw-84075p6 pw-84075p6 sleep mode sleep mode disable/reset disable/reset oc fault v cc v cc-rtn v cc v cc-rtn v dd v dd-rtn v dd v dd-rtn (4) auto reset auto reset auto reset regen clamp- vref a / d ch. 1 ua la ub lb uc lc a / d ch. 2 interrupt dsp motor controller position or velocity command resolver r/d converter vcc vdd vdd rtn i / o i / o i / o i / o i / o r22 c12 c13 r23 ov_adj ov_adj_high ov_adj_low r21 (4) notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/h-7, pw-82351 motor drive power supply , equation 1. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/h-7, pw-82351 motor drive power supply, equation 1 . 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 (load dump resistor), and r21 (ov adjust resistor) is application specific. (see ov adjust and rege n description for details) figure 9a. pw-8x075p6 position or velocity hook-up using dsp motor controller
14 +15v +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn r19 10k (8) r18 5k 0.01f c7 r17 10k 10m cr4 3.3v 1n746 cd4050 cd4049 c6 0.1f r15 10k r14 10k r13 10k +5v 19 11 18 14 hb hc ha hall supply +5v motor lm741 r11 r5 2k 1m r6 1k +5v command signal input 3.3v 1n746 cr5 10k (8) 10k 10k (8) 100 ? lm741 r10 r12 r22 r9 10k (8) r23 cd4049 1/6 1/6 1/6 1/6 q1(9) sleep mode v cc upper lower sc fault disable/reset v cc-rtn regen status ov adj v bus + output v bus - regen clamp+ upper lower sc fault oc fault v irsense v iref upper lower sc fault v iref v bus + output v bus - r sense + r sense - v bus + output v bus - r sense + r sense - pw-85075p6 pw-84075p6 pw-84075p6 hall rtn 10k v- v- 10k v- 10k uc-1625 sleep mode sleep mode disable/reset disable/reset oc fault (10) (10) (10) (11) (11) (11) (11) (11) (11) (11) (11) v cc v cc-rtn v cc v cc-rtn v dd v dd rtn v dd v dd rtn (4) auto reset auto reset auto reset regen clamp- v irsense_abs v irsense_abs v irsense v irsense_c v irsense_b icomp ha hb hc v iref v iref v iref current decommutation circuit (see fig. 9d) +15v -15v +5v r21 (4) ov_adj_high ov_adj_low notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/h-7, pw-82351 motor drive power supply , equation 1. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/h-7, pw-82351 motor drive power supply, equation 1 . 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 and r21 is application specific. 5. all resistors have a tolerance of 10%, unless otherwise specified. 6. the cd4050 converts the +15v logic output of the uc-1625 to +5v logic signals. 7. the cd4049 (or equivalent) inverts the upper signal from the uc-1625. 8. 1% or better, depending on required accuracy. 9. q 1 can be either irml2402 or irmu014 ir irld014. 10. these high impedance inputs and summing junctions of the operational amplifiers are highly sensitive to noise. 11. these grounds should be closely tied together to reduce ground noise effect. 12. connect hall sensor inputs to motor shaft position sensors that are 120 electrical degrees apart. motors with 60 electrical d egree position sensor coding can be used if one or two of the position sensor signals are inverted. figure 9b. pw-8x075p6 torque hook-up using uc-1625 motor controller
15 -vco vel -vsum cos -c +c bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 cb sin -s +s agnd +ref u3 -ref gnd a b bit/ inh/ el/ em/ c26 0.1f c27 22f c28 0.1f c29 22f 15 40 +5v r27 120k c25 560pf r28 2.8 m c24 56pf 9 8 7 6 5 10 11 13 14 12 19 20 4 r24 20k r25 20k r26 20k 1 2 r35 10k r29 0.1k r30 0.1k rs rc r31 10k r32 1k 2n2907 +15v 21 cr7 39 18 3 +5v vpp pgm oe ce a0 26 24 33 31 37 35 25 23 29 27 10 9 6 5 8 7 25 24 4 3 a1 a2 a3 a4 a5 a6 a7 a8 a9 20 22 c30 0.1f +5v 27 1 a10 a11 a12 21 23 2 00 01 02 03 04 05 06 07 26 24 33 31 37 35 27c64 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 74hct374 clk d7 +5v 1 11 r33 10k hc hb ha +15 -15 gnd gnd sense sin c22 0.1f +15v c23 0.1f -15v 13 8 10 11 2 1 c20 0.1f c21 0.1f +15v +15v 16 2 3 20 19 1 4 1 2 3 4 5 6 u6 el2009 16 17 -5v 22 ddc rdc-19220 hall outputs digital position & velocity information which can be used by the dsp (figure 8a) to close the position and/or velocity loops resolver inputs figure 9c. resolver to hall signal conversion circuit
16 figure 9d. pw-8x075p6 current decommutation circuit logic equations: /** inputs **/ ha /* phase a hall input, active high */ hb /* phase b hall input, active high */ hc /* phase c hall input, active high */ /** outputs **/ sw_gcomp_l /* positive gain compensation switch control, active low */ sw_nb_l /* switch control for negative b curre nt, active low */ sw_nc_l /* switch control for negative c current, active low */ sw_pb_l /* switch control for positive b current, active low */ sw_pc_l /* switch control for positive c current, active low */ /** equations **/ /** operator definition => ! = not, & = and, # = or **/ !sw_gcomp_l = ( !ha) !sw_nb_l = (ha & hb & !hc) !sw_nc_l =( ha & !hb) !sw_pb_l = (!ha & !hb & hc) !sw_pc_l = (!ha & hb) table [ha,hb,hc] => [sw_gcomp_l,sw_na_l,sw_nc_l, sw_pa_l,sw_pc_l] b 000 => b 01111; b 001 => b 01101; b 010 => b 01110; b 011 => b 01110; b 100 => b 11011; b 101 => b 11011; b 110 => b 10111; b 111 => b 11111; ia_n ic_p ia_p ic_n zero i_b_bipolar2 i_c_bipolar2 vref ic ib i_comp 0 0 0 0 0 0 0 0 0 u4b lf 147 5 6 4 11 7 + - v+ v- out u3 dg201 1 3 2 16 14 15 9 11 10 8 6 7 12 13 5 4 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 vl vdd gnd vss { rp } u4a lf 147 3 2 4 11 1 + - v+ v- out r6 4k { rn } u6 dg201 1 3 2 16 14 15 9 11 10 8 6 7 12 13 5 4 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 vl vdd gnd vss r8 4k r9 4k u4c lf147 10 9 4 11 8 + - v+ v- out { rp } r10 4k r11 4k { rf } r12 4k { rs } r7 4k c4 1000p { rn } { rf } c3 1000p sw_gcomp_l sw_nb_l sw_nc_l sw_pb_l sw_pc_l { rs } { rs }, { rp }, { rn } and vref relationships: ha hb hc ls132 54/74 ls08 54/74 ls08 ls132 ls132 54/74 +5v (common to all) gnd (common to all) +15v +15v +15v +5v +15v -15v +5v -15v -15v -15v -15v +15v
17 ordering information pw - 8 x 075 px - x x 0 process requirements: 0 = standard ddc procedures no burn-in 2 = high reliability processing with burn-in temperature grade/data requirements: 1 = -55 c to +125 c 3 = -0 c to +70 c 4 = -55 c to +125 c with variables test data 8 = 0 c to +70 c with variables test data 9 = -55 c to 85 c voltage rating 6 = 600v current rating 075 = 75a features 3 = standard ? bridge 4 = standard ? bridge w/ current sense 5 = standard ? bridge w/ regenerative voltage clamp
18 notes
19 notes
20 printed in the u.s.a. data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7420 headquarters - tel: (631) 567-5600 ext. 7420, fax: (631) 567-7358 west coast - tel: (714) 895-9777, fax: (714) 895-4988 southeast - tel: (703) 450-7900, fax: (703) 450-6610 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 sweden - tel: +46-(0)8-54490044, fax +46-(0)8-7550570 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com c2, 4/3/01

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